Optimal operating point estimator for hardware operating under a shared power/thermal constraint

ABSTRACT

Integrated circuits, or computer chips, typically include multiple hardware components (e.g. memory, processors, etc.) operating under a shared power (e.g. thermal) constraint that is sourced by one or more power sources for the chip. Typically, the hardware components can be individually configured to operate at certain states (e.g. to operate at a certain frequency by setting a clock speed for a clock dedicated to the hardware component). Thus, each hardware component can be configured to operate at an operating point that is determined to be optimal, usually in terms of achieving some desired goal for a specific application (e.g. frame rates for gaming, etc.). In the context of chip hardware that operates under a shared power/thermal constraint, a method, computer readable medium, and system are provided for determining the optimal operating point for the chip that takes into consideration both performance of the chip and power consumption by the chip.

FIELD OF THE INVENTION

The present invention relates to hardware components operating under ashared power (e.g. thermal) constraint, and in particular configuringoperation of hardware components operating under the shared powerconstraint.

BACKGROUND

Integrated circuits, or computer chips, typically include multiplehardware components operating under a shared power (e.g. thermal)constraint. The power/thermal constraint may be defined by the thermaldesign power (TDP) of the chip, and thus may be sourced by one or morepower sources for the chip [e.g. graphics processing unit (GPU) powersource, dynamic random access memory (DRAM) power source]. The hardwarecomponents that operate under the shared power/thermal constraint can bememory, processors, etc. and can be individually configured to operateat certain states within particular operating constraints of thehardware component. For example, memory can be configured to operate ata certain frequency, by setting a clock speed of a clock dedicated tothe memory. Similarly, a processor, such as a GPU, can be configured tooperate at a certain frequency, by setting a clock speed of a clockdedicated to the processor.

Due to the configurable nature of the above mentioned hardwarecomponents, algorithms have been developed to determine the particularconfiguration of a hardware component that achieves some desiredperformance for a particular application. For example, in a graphicsintensive application, such as a game, the processor can be configuredto operate at a high frequency in order to increase the frames persecond (FPS) computational capability of the processor which can improvethe graphics experience for a user. However, while current algorithmscan determine an optimal operating point of various hardware componentsin terms of performance in a particular application, these algorithmsare generally inefficient in optimally reducing the power consumed bythe hardware components at the “optimal” operating point. Thus, whileperformance may be improved, it will oftentimes be at the expense ofincreased power consumption.

There is a need for addressing these issues and/or other issuesassociated with the prior art.

SUMMARY

A method, computer readable medium, and system are disclosed for anoptimal operating point estimator for chip hardware operating under ashared power/thermal constraint, that takes into consideration bothperformance and power. In use, input is received that is associated withworkloads executed on a chip having two or more hardware components thatoperate under a shared power constraint. The input includes descriptionsof the workloads, performance metrics of each of the two or morehardware components when executing each of the workloads, and powerconsumption metrics for each of the workloads. Additionally, anartificial intelligence (AI) network is trained that correlates thedescriptions of the workloads, the performance metrics for each of theworkloads, and the power consumption by each of the workloads. Further,a selection is received of an optimization mode for the chip thatconsiders both performance and power. Still yet, the AI network is usedto determine an optimal operating point of the chip, according to theselected optimization mode. Moreover, the chip is configured to operateat the determined optimal operating point.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a flowchart of a method of an optimal operating pointestimator for chip hardware operating under a shared power/thermalconstraint, that takes into consideration both performance and power, inaccordance with an embodiment.

FIG. 2A illustrates a block diagram of the training phase of an optimaloperating point estimator, in accordance with an embodiment.

FIG. 2B illustrates a block diagram of a first mode for the deploymentphase of an optimal operating point estimator, in accordance with anembodiment.

FIG. 2C illustrates a block diagram of a second mode for the deploymentphase of an optimal operating point estimator, in accordance with anembodiment.

FIG. 2D illustrates a block diagram of a third mode for the deploymentphase of an optimal operating point estimator, in accordance with anembodiment.

FIG. 2E illustrates an efficiency curve for determining an optimaloperating point for the efficiency optimization mode, in accordance withan embodiment.

FIG. 2F illustrates state machine operation for an operating pointestimator, in accordance with an embodiment.

FIG. 3 illustrates a parallel processing unit, in accordance with anembodiment.

FIG. 4A illustrates a general processing cluster within the parallelprocessing unit of FIG. 3, in accordance with an embodiment.

FIG. 4B illustrates a memory partition unit of the parallel processingunit of FIG. 3, in accordance with an embodiment.

FIG. 5A illustrates the streaming multi-processor of FIG. 4A, inaccordance with an embodiment.

FIG. 5B is a conceptual diagram of a processing system implemented usingthe PPU of FIG. 3, in accordance with an embodiment.

FIG. 5C illustrates an exemplary system in which the variousarchitecture and/or functionality of the various previous embodimentsmay be implemented.

FIG. 6 is a conceptual diagram of a graphics processing pipelineimplemented by the PPU of FIG. 3, in accordance with an embodiment.

DETAILED DESCRIPTION

Integrated circuits, or computer chips, typically include multiplehardware components (e.g. memory, processors, etc.) operating under ashared power (e.g. thermal) constraint that is sourced by one or morepower sources for the chip. Typically, the hardware components can beindividually configured to operate at certain states (e.g. to operate ata certain frequency by setting a clock speed for a clock dedicated tothe hardware component). Thus, each hardware component can be configuredto operate at an operating point that is determined to be optimal,usually in terms of achieving some desired goal for a specificapplication (e.g. frame rates for gaming, etc.).

In the context of chip hardware that operates under a sharedpower/thermal constraint, a method, computer readable medium, and systemare provided for an optimal operating point estimator that determinesthe optimal operating point for the chip by taking into considerationboth performance of the chip and power consumption by the chip. Inparticular, the optimal operating point estimator is able to determine,for a combination of hardware components sharing the power/thermalconstraint, the optimal operating states and voltage state of thosehardware components which balance both performance and powerconsumption. Furthermore, the optimal operating point estimator employsan artificial intelligence (AI) network, which can be a machine learningnetwork or deep learning network, to make the optimal operating pointdetermination.

FIG. 1 illustrates a flowchart of a method 100 of an optimal operatingpoint estimator for chip hardware operating under a shared power/thermalconstraint, that takes into consideration both performance and power, inaccordance with an embodiment. In various embodiments, the method 100may be performed, and thus the optimal operating point estimatorimplemented, using a processing unit, a program, custom circuitry, or acombination of custom circuitry and a program. For example, the method100 may be executed by a GPU (graphics processing unit), CPU (centralprocessing unit), and/or in the context of the any of the hardwareembodiments described below. Furthermore, persons of ordinary skill inthe art will understand that any system that performs method 100 iswithin the scope and spirit of embodiments of the present invention.

In operation 102, input is received that is associated with workloadsexecuted on a chip having two or more hardware components that operateunder a shared power constraint. The input includes descriptions of theworkloads (e.g. for each workload, an indication of an applicationexecuting the workload, operations performed within the workload, dataon which the workload is performed, or any other description that can beused as a unique identifier of the workload), performance metrics (e.g.processing capabilities of the chip such as frame time, frames persecond, instructions per second, etc.) of each of the two or morehardware components when executing each of the workloads, and powerconsumption metrics (e.g. an amount of power consumed by each hardwarecomponent to perform the workload, a total amount of power consumed bythe two or more hardware components to perform the workload, etc.) foreach of the workloads.

In the context of the present description, the chip may be anyintegrated circuit (IC) having two or more hardware components thatoperate under a shared power (e.g. thermal) constraint and that arecapable of being utilized for executing workloads (e.g. processes,operations, etc.). For example, the hardware components may each bememory, such as dynamic random access memory (DRAM), and a processor,such as a graphics processing unit (GPU), a central processing unit(CPU), etc. Additionally, the shared power constraint refer to an amountof power available to the hardware components and may be sourced by oneor more power sources for the chip, such as a GPU power source, a DRAMpower source, etc.

As noted above, the input that is associated with workloads executed onthe chip is received (e.g. captured or otherwise accumulated). It shouldbe noted that the workloads can be executed for different applications,such as crypto currency applications, gaming applications, computeapplications, etc., and may be processes of those applications,operations performed by those applications, etc. In addition, the inputcan be accumulated by capture logic over a predefined window of time.For example, for graphics workloads involving frame renderingoperations, the input can be captured over an entire frame, and forcompute workloads involving computational operations or deep learningworkloads involving deep learning operations, the input can be capturedat a function call level or over a fixed period of time.

Additionally, in operation 104, an artificial intelligence (AI) networkis trained that correlates the descriptions of the workloads, theperformance metrics for each of the workloads, and the power consumptionby each of the workloads. The AI network may be a machine learningnetwork or machine learning model based on trees of shallow predictors,or a deep learning network, in various embodiments. In any case, thetrained AI network correlates each description of a particular workloadwith the power consumption metrics for the particular workload andperformance metrics for the particular workload.

Further, in operation 106, a selection is received of an optimizationmode for the chip that considers performance and power consumption. Inone embodiment the selection indicates: a parameter for which tooptimize operation of the chip (e.g. performance, power, or efficiency),and optionally a target value for the parameter. Thus, in oneembodiment, the selected optimization mode may be to optimize operationof the chip for performance, and the selection may include a targetvalue for the performance. In another embodiment, the selectedoptimization mode may be to optimize operation of the chip for power,and the selection may include a target value for the power. In yetanother embodiment, the selected optimization mode may be to optimizeoperation of the chip for efficiency. The selection may be made by auser, or automatically based on predetermined criteria, rules, or theparticular application for which the optimization is performed.

Still yet, in operation 108, the AI network is used to determine anoptimal operating point of the chip, according to the selectedoptimization mode. Using the AI network in this manner may includedeploying the AI network on the chip, in one embodiment. For example,the AI network may be deployed by running the AI network on the chip fordetermining the optimal operating point of the chip. As an option, theAI network may run by a CPU of the chip to determine the optimaloperating point of the chip. As another example, the AI network may berun by dedicated hardware of the chip for determining the optimaloperating point of the chip. Of course, its should be noted that the AInetwork may be used by any computer processor, computer logic, and/orcomputer program for determining the optimal operating point of thechip.

When the selected optimization mode is to optimize operation of the chipfor performance, the optimal operating point of the chip may bedetermined by identifying the target value for the performance and apower threshold, and using the AI network to determine the optimaloperating point for the chip to maximize performance without exceedingthe power threshold. As noted above, the target value for theperformance is specified when the optimization mode is selected. As anoption, the power threshold may also be specified when the optimizationmode is selected, or as another option may be specified separately (e.g.by a user, or automatically based on predetermined criteria, rules, theparticular application for which the optimization is performed, etc.).

In the context of the present embodiment, the optimal operating pointfor the chip includes operating states (e.g. clock frequencies) for eachhardware component of the two or more hardware components and a voltagestate (e.g. voltage input) for the two or more hardware components. Inorder to maximize performance without exceeding the power threshold, theoptimal operating point may be selected whereby operation of the chipcomes as close as possible to the target value for the performancewithout the power threshold being exceeded. As mentioned above, the AInetwork is used to determine the optimal operating point for the chip.This may include, for example, the above described correlations made bythe AI network being referenced to determine the operating states andvoltage state for the hardware components that maximize performancewithout exceeding the power threshold.

When the selected optimization mode is to optimize operation of the chipfor power, the optimal operating point of the chip may be determined byidentifying the target value for the power and a performance threshold,and using the AI network to determine the optimal operating point forthe chip to minimize power consumption without falling below theperformance threshold. As noted above, the target value for the power isspecified when the optimization mode is selected. As an option, theperformance threshold may also be specified when the optimization modeis selected, or as another option may be specified separately (e.g. by auser, or automatically based on predetermined criteria, rules, or theparticular application for which the optimization is performed).

Again, in the context of the present embodiment, the optimal operatingpoint for the chip includes operating states (e.g. clock frequencies)for each hardware component of the two or more hardware components and avoltage state (e.g. voltage input) for the two or more hardwarecomponents. In order to minimize power consumption without falling belowthe performance threshold, the optimal operating point may be selectedwhereby operation of the chip comes as close as possible to the targetvalue for the power without falling below the performance threshold. Asmentioned above, the AI network is used to determine the optimaloperating point for the chip. This may include, for example, the abovedescribed correlations made by the AI network being referenced todetermine the operating states and voltage state for the hardwarecomponents that minimize power consumption without falling below theperformance threshold.

When the selected optimization mode is to optimize operation of the chipfor efficiency, the optimal operating point of the chip may bedetermined by identifying an efficiency threshold, where the efficiencythreshold is defined based on a change in performance in relation to achange in power consumption, and further using the AI network todetermine the optimal operating point for the chip to maximizeperformance without falling below the efficiency threshold. For example,the determined operating point may be one that provides an optimalperformance at an operating power, where the operating point isdetermined based on performance and the point on an efficiency curvewhere the efficiency diminishes beyond a certain set operating voltageand frequency. Again, the optimal operating point for the chip mayinclude operating states for each hardware component of the two or morehardware components and a voltage state for the two or more hardwarecomponents.

Moreover, in operation 110, the chip is configured to operate at thedetermined optimal operating point. In other words, the two or morehardware are configured to operate at the determined respectiveoperating states and at the voltage state.

In this way, in the context of the chip which operates under a sharedpower/thermal constraint, the method 100 may determine the optimaloperating point for the chip by taking into consideration bothperformance of the chip and power consumption by the chip. Inparticular, for a combination of hardware components of the chip sharingthe power/thermal constraint, the optimal operating states and voltagestate of those hardware components may be determined which balance bothperformance and power consumption.

For example, the operating point estimator may allow the GPU of a chipto save power while delivering similar performance to those provided byprior art systems, thus improving battery life, or lifetime power costfor plugged-in systems. As another example, for power constrained casessuch as chips operating under Nvidia's Max-Q operating conditions, theoperating point estimator can improve performance by optimal selectionof the operating point for the chip, depending on the nature of theworkload. As yet another example, in deep learning applications wherethere are memory bottlenecked phases (similar to mining), the operatingpoint estimator may lower performance and reduce power during thosephases and then boost performance and power during other phases toimprove overall performance under the same power budget.

Additionally, by using the AI network, the operating point of the chipcan be rapidly adjusted to reach the target performance or power value.The maximum speed of change in the operating point of the chip maydepend on the latency of the AI network, and the latency may be reducedwhen deployed on dedicated hardware of the chip. Further, by adjustingthe operating point as needed, static power limits for certain chips maybe avoided and static chip configurations per application may also beavoided.

The operating point estimator may also correctly cap clocks of thehardware components in cases where bottlenecks do not allow theperformance to actually scale with higher clock frequencies, which willensure that power is not wasted without improving performance. Stillyet, since the operating point estimator utilizes fine-grain telemetryfrom the chip (e.g. for workloads per frame, etc.) the operating pointestimator can accurately determine the optimal operating point of thechip, such for chips operating under Nvidia's Max-Q operatingconditions.

More illustrative information will now be set forth regarding variousoptional architectures and features with which the foregoing frameworkmay be implemented, per the desires of the user. It should be stronglynoted that the following information is set forth for illustrativepurposes and should not be construed as limiting in any manner. Any ofthe following features may be optionally incorporated with or withoutthe exclusion of other features described.

FIG. 2A illustrates a block diagram of the training phase of an optimaloperating point estimator, in accordance with an embodiment. As anoption, the training phase may be performed offline with respect to thechip for which the training phase is being performed.

Initially, the optimal operating point estimator 126 executes a trainingphase, in which the AI network 128 is trained for a chip having two ormore hardware components that operate under a shared power constraint.The hardware components can be memory (e.g. DRAM), a processing unit(e.g. GPU etc.), or any other hardware integrated within the chip. TheAI network 128 is trained by the optimal operating point estimator 126using inputs associated with workloads executed on the chip. The inputsinclude descriptions of the workloads 120, performance metrics (e.g.frame times, etc.) of each of the hardware components when executingeach of the workloads 122, and power consumption metrics (e.g. powerconsumption by each hardware component, total power consumption, etc.)for each of the workloads 124.

It should be noted that the workloads can be executed for differentapplications, such as crypto currency applications, gaming applications,compute applications, etc. In addition, the inputs 120, 122, 124 can beaccumulated by capture logic of the operating point estimator 126 over apredefined window of time. For example, for graphics workloads, theinputs 120, 122, 124 can be captured over an entire frame, and forcompute or deep learning workloads, the inputs 120, 122, 124 can becaptured at a function call level or over a fixed period of time.

In one embodiment, the AI network 128 is trained to correlate particularworkload descriptions with power consumption metrics and performancemetrics. For example, the AI network 128 may learn the power consumptionby the chip for a particular workload (specified by description) as wellas the performance of the chip for the particular workload. In thisembodiment, for a given workload description, the trained AI network 128can output the power consumption metrics and performance metricscorrelated therewith.

In another embodiment, in addition to training the AI network 128 tocorrelate particular workload descriptions with power consumptionmetrics and performance metrics, as described above, the AI network 128may also be trained to determine, based on the inputs 120, 122, 124, anoptimal operating point for the chip. For example, for each possibleoptimization mode for the chip, the AI network 128 may learn the optimaloperating point of the chip for a particular workload, based on thepower consumption metrics and performance metrics correlated therewith.In this embodiment, for a given workload description and optimizationmode, the trained AI network 128 can output the optimal operating pointfor the chip.

In conjunction with the training phase, the optimal operating pointestimator 126 may receive a selection of an optimization mode (notshown) for the chip, namely an indication of whether to optimizeoperation of the chip for performance, power, or efficiency. Theselected optimization mode may also indicate a threshold value. Forexample, when the optimization mode indicates to optimize operation ofthe chip for performance, the threshold value may be for power, suchthat performance of the chip is to be maximized towards a target valuewithout exceeding the power threshold. As another example, when theoptimization mode indicates to optimize operation of the chip for power,the threshold value may be for performance, such that power consumptionby the chip is minimized toward a target value without falling below theperformance threshold. As yet another embodiment, when the optimizationmode indicates to optimize operation of the chip for efficiency, thethreshold value may be for the efficiency (change in performance/changein power), such that performance of the chip is to be maximized (e.g.toward a target performance value) without falling below the efficiencythreshold. Of course, it should be noted that in other embodiments theoptimization mode may be received by the optimal operating pointestimator 126 independent of the training phase.

After the training phase, the optimal operating point estimator 126 thenexecutes a deployment phase, in which the AI network 128 is deployed onthe chip to determine the optimal operating point of the chip and toconfigure the chip accordingly. Optionally, the deployment phase may beperformed online. For example, the deployment phase can be executed assoftware by a CPU of the chip, or can be executed through dedicatedhardware on the chip.

By applying the concept of temporal locality, where workloads executedin close temporal proximity are assumed to be similar (e.g. exhibitsimilar properties), the operating point estimator 126 uses adescription of one or more prior workloads executed by the chip todetermine from the AI network 128 the optimal operating point of thechip to be employed when executing a subsequent workload. To this end,the deployment phase, or at least the determination of the optimaloperating point and the corresponding configuration of the chip, can berepeated for each new workload (e.g. frame). As another option, thedeployment phase, or at least the determination of the optimal operatingpoint and the corresponding configuration of the chip, can be repeatedduring workload execution at various predefined operating points withinan application.

Various embodiments of the deployment phase will now be described withreference to FIGS. 2B-2D.

FIG. 2B illustrates a block diagram of a first mode for the deploymentphase of an optimal operating point estimator, in accordance with anembodiment. In the first mode for the deployment phase, the optimaloperating point estimator uses a controller 136 independent of the AInetwork 128 to determine the optimal operating point of the chip and toconfigure the chip accordingly.

As shown, the AI network 128 is queried with input including adescription of a previous workload executed on the chip 130, the actualoperating point of the chip when executing the previous workload 131,and select neighboring operating points for the chip 132. The AI network128 outputs, in response the query, a list 134 of possible performancemetrics and power metrics that correspond to each of the input operatingpoints. The controller 136, external to the AI network 128, then selectsthe optimal operating point 140 from the list 134 output from the AInetwork 128, based on the selected optimization mode 138. The controller136 further configures the chip to operate at the optimal operatingpoint 140, or otherwise causes other hardware and/or software toconfigure the chip to operate at the optimal operating point 140.

FIG. 2C illustrates a block diagram of a second mode for the deploymentphase of an optimal operating point estimator, in accordance with anembodiment. The second mode for the deployment phase operates the sameas the first mode for the deployment phase described in FIG. 2B, exceptthe AI network 128 outputs, in response the query, a list 134 ofpossible performance metrics OR power metrics that correspond to each ofthe input operating points. The controller 136, external to the AInetwork 128, then selects one of the metrics in the list and uses thismetric to setup the other operating point parameter, based on theselected optimization mode 138. For example, if the AI network 128outputs a list of operating frequencies, then the controller may selectone of the operating frequencies in the list, and then determine fromthe selected operating frequency a corresponding operating voltage. Thecontroller 136 further configures the chip to operate at the optimaloperating point 140, or otherwise causes other hardware and/or softwareto configure the chip to operate at the optimal operating point 140.

FIG. 2D illustrates a block diagram of a third mode for the deploymentphase of an optimal operating point estimator, in accordance with anembodiment. In the third mode for the deployment phase, the AI network128 determines the optimal operating point of the chip and configuresthe chip accordingly.

During deployment of the AI network 128, the AI network 128 is queriedwith input including a description of a previous workload executed onthe chip 130 and the optimization mode 138. The AI network 128 thenoutputs, in response the query, the optimal operating point 140 for thechip. The optimal operating point 140 output by the AI network 128received by hardware and/or software which configures the chip tooperate at the optimal operating point 140.

FIG. 2E illustrates an efficiency curve for determining an optimaloperating point for the efficiency optimization mode described above. Asshown, the operating point that provides an optimal performance at anoperating power is determined, where the operating point is determinedbased on performance and a point on the efficiency curve where theefficiency, or increase in performance (dPerf) relative the change inpower consumption (dPower), diminishes beyond a certain set operatingvoltage and frequency. In FIG. 2E, this point is indicated by the slopeof the tangent on the efficiency curve.

FIG. 2F illustrates state machine operation for an operating pointestimator, in accordance with an embodiment. After an initial Ready(Idle) state 150, an execute command is issued to Accumulate Data 152.The Data includes descriptions of workloads most recently executed onthe chip, performance metrics of each of hardware components whenexecuting each of the workloads, and power consumption metrics for eachof the workloads. In the embodiment shown, the Data is accumulated overa certain number of frames (e.g. frame_count).

Once the Data is accumulated, a Data Read 154 is performed where theaccumulated Data is read from memory. Once the Data is read, an AIInference 156 is made using the read Data. The AI Inference 156 may berepeated to generate a list of possible performance metrics and powermetrics that correspond to the Data. For example, the AI Inference 156may be performed for an actual operating point of the chip whenexecuting a previous workload, and select neighboring operating pointsfor the chip. The AI Inference 156 may thus include a list of possibleperformance metrics and power metrics that correspond to each of theoperating points included in the Data. A controller selects, from theoutput of the AI Inference 156, an optimal V-F Update 158 for the chip,which is the optimal operating point (voltage and frequency) for thechip, and the chip is transitioned to the selected optimal operatingpoint. Once the chip is transitioned to the selected optimal operatingpoint, the state machine returns to the Ready (Idle) state 150 and waitsfor the next execute command.

Parallel Processing Architecture

FIG. 3 illustrates a parallel processing unit (PPU) 300, in accordancewith an embodiment. In an embodiment, the PPU 300 is a multi-threadedprocessor that is implemented on one or more integrated circuit devices.The PPU 300 is a latency hiding architecture designed to process manythreads in parallel. A thread (e.g., a thread of execution) is aninstantiation of a set of instructions configured to be executed by thePPU 300. In an embodiment, the PPU 300 is a graphics processing unit(GPU) configured to implement a graphics rendering pipeline forprocessing three-dimensional (3D) graphics data in order to generatetwo-dimensional (2D) image data for display on a display device such asa liquid crystal display (LCD) device. In other embodiments, the PPU 300may be utilized for performing general-purpose computations. While oneexemplary parallel processor is provided herein for illustrativepurposes, it should be strongly noted that such processor is set forthfor illustrative purposes only, and that any processor may be employedto supplement and/or substitute for the same.

One or more PPUs 300 may be configured to accelerate thousands of HighPerformance Computing (HPC), data center, and machine learningapplications. The PPU 300 may be configured to accelerate numerous deeplearning systems and applications including autonomous vehicleplatforms, deep learning, high-accuracy speech, image, and textrecognition systems, intelligent video analytics, molecular simulations,drug discovery, disease diagnosis, weather forecasting, big dataanalytics, astronomy, molecular dynamics simulation, financial modeling,robotics, factory automation, real-time language translation, onlinesearch optimizations, and personalized user recommendations, and thelike.

As shown in FIG. 3, the PPU 300 includes an Input/Output (I/O) unit 305,a front end unit 315, a scheduler unit 320, a work distribution unit325, a hub 330, a crossbar (Xbar) 370, one or more general processingclusters (GPCs) 350, and one or more partition units 380. The PPU 300may be connected to a host processor or other PPUs 300 via one or morehigh-speed NVLink 310 interconnect. The PPU 300 may be connected to ahost processor or other peripheral devices via an interconnect 302. ThePPU 300 may also be connected to a local memory comprising a number ofmemory devices 304. In an embodiment, the local memory may comprise anumber of dynamic random access memory (DRAM) devices. The DRAM devicesmay be configured as a high-bandwidth memory (HBM) subsystem, withmultiple DRAM dies stacked within each device.

The NVLink 310 interconnect enables systems to scale and include one ormore PPUs 300 combined with one or more CPUs, supports cache coherencebetween the PPUs 300 and CPUs, and CPU mastering. Data and/or commandsmay be transmitted by the NVLink 310 through the hub 330 to/from otherunits of the PPU 300 such as one or more copy engines, a video encoder,a video decoder, a power management unit, etc. (not explicitly shown).The NVLink 310 is described in more detail in conjunction with FIG. 5B.

The I/O unit 305 is configured to transmit and receive communications(e.g., commands, data, etc.) from a host processor (not shown) over theinterconnect 302. The I/O unit 305 may communicate with the hostprocessor directly via the interconnect 302 or through one or moreintermediate devices such as a memory bridge. In an embodiment, the I/Ounit 305 may communicate with one or more other processors, such as oneor more the PPUs 300 via the interconnect 302. In an embodiment, the I/Ounit 305 implements a Peripheral Component Interconnect Express (PCIe)interface for communications over a PCIe bus and the interconnect 302 isa PCIe bus. In alternative embodiments, the I/O unit 305 may implementother types of well-known interfaces for communicating with externaldevices.

The I/O unit 305 decodes packets received via the interconnect 302. Inan embodiment, the packets represent commands configured to cause thePPU 300 to perform various operations. The I/O unit 305 transmits thedecoded commands to various other units of the PPU 300 as the commandsmay specify. For example, some commands may be transmitted to the frontend unit 315. Other commands may be transmitted to the hub 330 or otherunits of the PPU 300 such as one or more copy engines, a video encoder,a video decoder, a power management unit, etc. (not explicitly shown).In other words, the I/O unit 305 is configured to route communicationsbetween and among the various logical units of the PPU 300.

In an embodiment, a program executed by the host processor encodes acommand stream in a buffer that provides workloads to the PPU 300 forprocessing. A workload may comprise several instructions and data to beprocessed by those instructions. The buffer is a region in a memory thatis accessible (e.g., read/write) by both the host processor and the PPU300. For example, the I/O unit 305 may be configured to access thebuffer in a system memory connected to the interconnect 302 via memoryrequests transmitted over the interconnect 302. In an embodiment, thehost processor writes the command stream to the buffer and thentransmits a pointer to the start of the command stream to the PPU 300.The front end unit 315 receives pointers to one or more command streams.The front end unit 315 manages the one or more streams, reading commandsfrom the streams and forwarding commands to the various units of the PPU300.

The front end unit 315 is coupled to a scheduler unit 320 thatconfigures the various GPCs 350 to process tasks defined by the one ormore streams. The scheduler unit 320 is configured to track stateinformation related to the various tasks managed by the scheduler unit320. The state may indicate which GPC 350 a task is assigned to, whetherthe task is active or inactive, a priority level associated with thetask, and so forth. The scheduler unit 320 manages the execution of aplurality of tasks on the one or more GPCs 350.

The scheduler unit 320 is coupled to a work distribution unit 325 thatis configured to dispatch tasks for execution on the GPCs 350. The workdistribution unit 325 may track a number of scheduled tasks receivedfrom the scheduler unit 320. In an embodiment, the work distributionunit 325 manages a pending task pool and an active task pool for each ofthe GPCs 350. The pending task pool may comprise a number of slots(e.g., 32 slots) that contain tasks assigned to be processed by aparticular GPC 350. The active task pool may comprise a number of slots(e.g., 4 slots) for tasks that are actively being processed by the GPCs350. As a GPC 350 finishes the execution of a task, that task is evictedfrom the active task pool for the GPC 350 and one of the other tasksfrom the pending task pool is selected and scheduled for execution onthe GPC 350. If an active task has been idle on the GPC 350, such aswhile waiting for a data dependency to be resolved, then the active taskmay be evicted from the GPC 350 and returned to the pending task poolwhile another task in the pending task pool is selected and scheduledfor execution on the GPC 350.

The work distribution unit 325 communicates with the one or more GPCs350 via XBar 370. The XBar 370 is an interconnect network that couplesmany of the units of the PPU 300 to other units of the PPU 300. Forexample, the XBar 370 may be configured to couple the work distributionunit 325 to a particular GPC 350. Although not shown explicitly, one ormore other units of the PPU 300 may also be connected to the XBar 370via the hub 330.

The tasks are managed by the scheduler unit 320 and dispatched to a GPC350 by the work distribution unit 325. The GPC 350 is configured toprocess the task and generate results. The results may be consumed byother tasks within the GPC 350, routed to a different GPC 350 via theXBar 370, or stored in the memory 304. The results can be written to thememory 304 via the partition units 380, which implement a memoryinterface for reading and writing data to/from the memory 304. Theresults can be transmitted to another PPU 304 or CPU via the NVLink 310.In an embodiment, the PPU 300 includes a number U of partition units 380that is equal to the number of separate and distinct memory devices 304coupled to the PPU 300. A partition unit 380 will be described in moredetail below in conjunction with FIG. 4B.

In an embodiment, a host processor executes a driver kernel thatimplements an application programming interface (API) that enables oneor more applications executing on the host processor to scheduleoperations for execution on the PPU 300. In an embodiment, multiplecompute applications are simultaneously executed by the PPU 300 and thePPU 300 provides isolation, quality of service (QoS), and independentaddress spaces for the multiple compute applications. An application maygenerate instructions (e.g., API calls) that cause the driver kernel togenerate one or more tasks for execution by the PPU 300. The driverkernel outputs tasks to one or more streams being processed by the PPU300. Each task may comprise one or more groups of related threads,referred to herein as a warp. In an embodiment, a warp comprises 32related threads that may be executed in parallel. Cooperating threadsmay refer to a plurality of threads including instructions to performthe task and that may exchange data through shared memory. Threads andcooperating threads are described in more detail in conjunction withFIG. 5A.

FIG. 4A illustrates a GPC 350 of the PPU 300 of FIG. 3, in accordancewith an embodiment. As shown in FIG. 4A, each GPC 350 includes a numberof hardware units for processing tasks. In an embodiment, each GPC 350includes a pipeline manager 410, a pre-raster operations unit (PROP)415, a raster engine 425, a work distribution crossbar (WDX) 480, amemory management unit (MMU) 490, and one or more Data ProcessingClusters (DPCs) 420. It will be appreciated that the GPC 350 of FIG. 4Amay include other hardware units in lieu of or in addition to the unitsshown in FIG. 4A.

In an embodiment, the operation of the GPC 350 is controlled by thepipeline manager 410. The pipeline manager 410 manages the configurationof the one or more DPCs 420 for processing tasks allocated to the GPC350. In an embodiment, the pipeline manager 410 may configure at leastone of the one or more DPCs 420 to implement at least a portion of agraphics rendering pipeline. For example, a DPC 420 may be configured toexecute a vertex shader program on the programmable streamingmultiprocessor (SM) 440. The pipeline manager 410 may also be configuredto route packets received from the work distribution unit 325 to theappropriate logical units within the GPC 350. For example, some packetsmay be routed to fixed function hardware units in the PROP 415 and/orraster engine 425 while other packets may be routed to the DPCs 420 forprocessing by the primitive engine 435 or the SM 440. In an embodiment,the pipeline manager 410 may configure at least one of the one or moreDPCs 420 to implement a neural network model and/or a computingpipeline.

The PROP unit 415 is configured to route data generated by the rasterengine 425 and the DPCs 420 to a Raster Operations (ROP) unit, describedin more detail in conjunction with FIG. 4B. The PROP unit 415 may alsobe configured to perform optimizations for color blending, organizepixel data, perform address translations, and the like.

The raster engine 425 includes a number of fixed function hardware unitsconfigured to perform various raster operations. In an embodiment, theraster engine 425 includes a setup engine, a coarse raster engine, aculling engine, a clipping engine, a fine raster engine, and a tilecoalescing engine. The setup engine receives transformed vertices andgenerates plane equations associated with the geometric primitivedefined by the vertices. The plane equations are transmitted to thecoarse raster engine to generate coverage information (e.g., an x,ycoverage mask for a tile) for the primitive. The output of the coarseraster engine is transmitted to the culling engine where fragmentsassociated with the primitive that fail a z-test are culled, andtransmitted to a clipping engine where fragments lying outside a viewingfrustum are clipped. Those fragments that survive clipping and cullingmay be passed to the fine raster engine to generate attributes for thepixel fragments based on the plane equations generated by the setupengine. The output of the raster engine 425 comprises fragments to beprocessed, for example, by a fragment shader implemented within a DPC420.

Each DPC 420 included in the GPC 350 includes an M-Pipe Controller (MPC)430, a primitive engine 435, and one or more SMs 440. The MPC 430controls the operation of the DPC 420, routing packets received from thepipeline manager 410 to the appropriate units in the DPC 420. Forexample, packets associated with a vertex may be routed to the primitiveengine 435, which is configured to fetch vertex attributes associatedwith the vertex from the memory 304. In contrast, packets associatedwith a shader program may be transmitted to the SM 440.

The SM 440 comprises a programmable streaming processor that isconfigured to process tasks represented by a number of threads. Each SM440 is multi-threaded and configured to execute a plurality of threads(e.g., 32 threads) from a particular group of threads concurrently. Inan embodiment, the SM 440 implements a SIMD (Single-Instruction,Multiple-Data) architecture where each thread in a group of threads(e.g., a warp) is configured to process a different set of data based onthe same set of instructions. All threads in the group of threadsexecute the same instructions. In another embodiment, the SM 440implements a SIMT (Single-Instruction, Multiple Thread) architecturewhere each thread in a group of threads is configured to process adifferent set of data based on the same set of instructions, but whereindividual threads in the group of threads are allowed to diverge duringexecution. In an embodiment, a program counter, call stack, andexecution state is maintained for each warp, enabling concurrencybetween warps and serial execution within warps when threads within thewarp diverge. In another embodiment, a program counter, call stack, andexecution state is maintained for each individual thread, enabling equalconcurrency between all threads, within and between warps. Whenexecution state is maintained for each individual thread, threadsexecuting the same instructions may be converged and executed inparallel for maximum efficiency. The SM 440 will be described in moredetail below in conjunction with FIG. 5A.

The MMU 490 provides an interface between the GPC 350 and the partitionunit 380. The MMU 490 may provide translation of virtual addresses intophysical addresses, memory protection, and arbitration of memoryrequests. In an embodiment, the MMU 490 provides one or more translationlookaside buffers (TLBs) for performing translation of virtual addressesinto physical addresses in the memory 304.

FIG. 4B illustrates a memory partition unit 380 of the PPU 300 of FIG.3, in accordance with an embodiment. As shown in FIG. 4B, the memorypartition unit 380 includes a Raster Operations (ROP) unit 450, a leveltwo (L2) cache 460, and a memory interface 470. The memory interface 470is coupled to the memory 304. Memory interface 470 may implement 32, 64,128, 1024-bit data buses, or the like, for high-speed data transfer. Inan embodiment, the PPU 300 incorporates U memory interfaces 470, onememory interface 470 per pair of partition units 380, where each pair ofpartition units 380 is connected to a corresponding memory device 304.For example, PPU 300 may be connected to up to Y memory devices 304,such as high bandwidth memory stacks or graphics double-data-rate,version 5, synchronous dynamic random access memory, or other types ofpersistent storage.

In an embodiment, the memory interface 470 implements an HBM2 memoryinterface and Y equals half U. In an embodiment, the HBM2 memory stacksare located on the same physical package as the PPU 300, providingsubstantial power and area savings compared with conventional GDDR5SDRAM systems. In an embodiment, each HBM2 stack includes four memorydies and Y equals 4, with HBM2 stack including two 128-bit channels perdie for a total of 8 channels and a data bus width of 1024 bits.

In an embodiment, the memory 304 supports Single-Error CorrectingDouble-Error Detecting (SECDED) Error Correction Code (ECC) to protectdata. ECC provides higher reliability for compute applications that aresensitive to data corruption. Reliability is especially important inlarge-scale cluster computing environments where PPUs 300 process verylarge datasets and/or run applications for extended periods.

In an embodiment, the PPU 300 implements a multi-level memory hierarchy.In an embodiment, the memory partition unit 380 supports a unifiedmemory to provide a single unified virtual address space for CPU and PPU300 memory, enabling data sharing between virtual memory systems. In anembodiment the frequency of accesses by a PPU 300 to memory located onother processors is traced to ensure that memory pages are moved to thephysical memory of the PPU 300 that is accessing the pages morefrequently. In an embodiment, the NVLink 310 supports addresstranslation services allowing the PPU 300 to directly access a CPU'spage tables and providing full access to CPU memory by the PPU 300.

In an embodiment, copy engines transfer data between multiple PPUs 300or between PPUs 300 and CPUs. The copy engines can generate page faultsfor addresses that are not mapped into the page tables. The memorypartition unit 380 can then service the page faults, mapping theaddresses into the page table, after which the copy engine can performthe transfer. In a conventional system, memory is pinned (e.g.,non-pageable) for multiple copy engine operations between multipleprocessors, substantially reducing the available memory. With hardwarepage faulting, addresses can be passed to the copy engines withoutworrying if the memory pages are resident, and the copy process istransparent.

Data from the memory 304 or other system memory may be fetched by thememory partition unit 380 and stored in the L2 cache 460, which islocated on-chip and is shared between the various GPCs 350. As shown,each memory partition unit 380 includes a portion of the L2 cache 460associated with a corresponding memory device 304. Lower level cachesmay then be implemented in various units within the GPCs 350. Forexample, each of the SMs 440 may implement a level one (L1) cache. TheL1 cache is private memory that is dedicated to a particular SM 440.Data from the L2 cache 460 may be fetched and stored in each of the L1caches for processing in the functional units of the SMs 440. The L2cache 460 is coupled to the memory interface 470 and the XBar 370.

The ROP unit 450 performs graphics raster operations related to pixelcolor, such as color compression, pixel blending, and the like. The ROPunit 450 also implements depth testing in conjunction with the rasterengine 425, receiving a depth for a sample location associated with apixel fragment from the culling engine of the raster engine 425. Thedepth is tested against a corresponding depth in a depth buffer for asample location associated with the fragment. If the fragment passes thedepth test for the sample location, then the ROP unit 450 updates thedepth buffer and transmits a result of the depth test to the rasterengine 425. It will be appreciated that the number of partition units380 may be different than the number of GPCs 350 and, therefore, eachROP unit 450 may be coupled to each of the GPCs 350. The ROP unit 450tracks packets received from the different GPCs 350 and determines whichGPC 350 that a result generated by the ROP unit 450 is routed to throughthe Xbar 370. Although the ROP unit 450 is included within the memorypartition unit 380 in FIG. 4B, in other embodiment, the ROP unit 450 maybe outside of the memory partition unit 380. For example, the ROP unit450 may reside in the GPC 350 or another unit.

FIG. 5A illustrates the streaming multi-processor 440 of FIG. 4A, inaccordance with an embodiment. As shown in FIG. 5A, the SM 440 includesan instruction cache 505, one or more scheduler units 510, a registerfile 520, one or more processing cores 550, one or more special functionunits (SFUs) 552, one or more load/store units (LSUs) 554, aninterconnect network 580, a shared memory/L1 cache 570.

As described above, the work distribution unit 325 dispatches tasks forexecution on the GPCs 350 of the PPU 300. The tasks are allocated to aparticular DPC 420 within a GPC 350 and, if the task is associated witha shader program, the task may be allocated to an SM 440. The schedulerunit 510 receives the tasks from the work distribution unit 325 andmanages instruction scheduling for one or more thread blocks assigned tothe SM 440. The scheduler unit 510 schedules thread blocks for executionas warps of parallel threads, where each thread block is allocated atleast one warp. In an embodiment, each warp executes 32 threads. Thescheduler unit 510 may manage a plurality of different thread blocks,allocating the warps to the different thread blocks and then dispatchinginstructions from the plurality of different cooperative groups to thevarious functional units (e.g., cores 550, SFUs 552, and LSUs 554)during each clock cycle.

Cooperative Groups is a programming model for organizing groups ofcommunicating threads that allows developers to express the granularityat which threads are communicating, enabling the expression of richer,more efficient parallel decompositions. Cooperative launch APIs supportsynchronization amongst thread blocks for the execution of parallelalgorithms. Conventional programming models provide a single, simpleconstruct for synchronizing cooperating threads: a barrier across allthreads of a thread block (e.g., the syncthreads( ) function). However,programmers would often like to define groups of threads at smaller thanthread block granularities and synchronize within the defined groups toenable greater performance, design flexibility, and software reuse inthe form of collective group-wide function interfaces.

Cooperative Groups enables programmers to define groups of threadsexplicitly at sub-block (e.g., as small as a single thread) andmulti-block granularities, and to perform collective operations such assynchronization on the threads in a cooperative group. The programmingmodel supports clean composition across software boundaries, so thatlibraries and utility functions can synchronize safely within theirlocal context without having to make assumptions about convergence.Cooperative Groups primitives enable new patterns of cooperativeparallelism, including producer-consumer parallelism, opportunisticparallelism, and global synchronization across an entire grid of threadblocks.

A dispatch unit 515 is configured to transmit instructions to one ormore of the functional units. In the embodiment, the scheduler unit 510includes two dispatch units 515 that enable two different instructionsfrom the same warp to be dispatched during each clock cycle. Inalternative embodiments, each scheduler unit 510 may include a singledispatch unit 515 or additional dispatch units 515.

Each SM 440 includes a register file 520 that provides a set ofregisters for the functional units of the SM 440. In an embodiment, theregister file 520 is divided between each of the functional units suchthat each functional unit is allocated a dedicated portion of theregister file 520. In another embodiment, the register file 520 isdivided between the different warps being executed by the SM 440. Theregister file 520 provides temporary storage for operands connected tothe data paths of the functional units.

Each SM 440 comprises L processing cores 550. In an embodiment, the SM440 includes a large number (e.g., 128, etc.) of distinct processingcores 550. Each core 550 may include a fully-pipelined,single-precision, double-precision, and/or mixed precision processingunit that includes a floating point arithmetic logic unit and an integerarithmetic logic unit. In an embodiment, the floating point arithmeticlogic units implement the IEEE 754-2008 standard for floating pointarithmetic. In an embodiment, the cores 550 include 64 single-precision(32-bit) floating point cores, 64 integer cores, 32 double-precision(64-bit) floating point cores, and 8 tensor cores.

Tensor cores configured to perform matrix operations, and, in anembodiment, one or more tensor cores are included in the cores 550. Inparticular, the tensor cores are configured to perform deep learningmatrix arithmetic, such as convolution operations for neural networktraining and inferencing. In an embodiment, each tensor core operates ona 4×4 matrix and performs a matrix multiply and accumulate operationD=A×B+C, where A, B, C, and D are 4×4 matrices.

In an embodiment, the matrix multiply inputs A and B are 16-bit floatingpoint matrices, while the accumulation matrices C and D may be 16-bitfloating point or 32-bit floating point matrices. Tensor Cores operateon 16-bit floating point input data with 32-bit floating pointaccumulation. The 16-bit floating point multiply requires 64 operationsand results in a full precision product that is then accumulated using32-bit floating point addition with the other intermediate products fora 4×4×4 matrix multiply. In practice, Tensor Cores are used to performmuch larger two-dimensional or higher dimensional matrix operations,built up from these smaller elements. An API, such as CUDA 9 C++ API,exposes specialized matrix load, matrix multiply and accumulate, andmatrix store operations to efficiently use Tensor Cores from a CUDA-C++program. At the CUDA level, the warp-level interface assumes 16×16 sizematrices spanning all 32 threads of the warp.

Each SM 440 also comprises M SFUs 552 that perform special functions(e.g., attribute evaluation, reciprocal square root, and the like). Inan embodiment, the SFUs 552 may include a tree traversal unit configuredto traverse a hierarchical tree data structure. In an embodiment, theSFUs 552 may include texture unit configured to perform texture mapfiltering operations. In an embodiment, the texture units are configuredto load texture maps (e.g., a 2D array of texels) from the memory 304and sample the texture maps to produce sampled texture values for use inshader programs executed by the SM 440. In an embodiment, the texturemaps are stored in the shared memory/L1 cache 470. The texture unitsimplement texture operations such as filtering operations using mip-maps(e.g., texture maps of varying levels of detail). In an embodiment, eachSM 340 includes two texture units.

Each SM 440 also comprises N LSUs 554 that implement load and storeoperations between the shared memory/L1 cache 570 and the register file520. Each SM 440 includes an interconnect network 580 that connects eachof the functional units to the register file 520 and the LSU 554 to theregister file 520, shared memory/L1 cache 570. In an embodiment, theinterconnect network 580 is a crossbar that can be configured to connectany of the functional units to any of the registers in the register file520 and connect the LSUs 554 to the register file and memory locationsin shared memory/L1 cache 570.

The shared memory/L1 cache 570 is an array of on-chip memory that allowsfor data storage and communication between the SM 440 and the primitiveengine 435 and between threads in the SM 440. In an embodiment, theshared memory/L1 cache 570 comprises 128 KB of storage capacity and isin the path from the SM 440 to the partition unit 380. The sharedmemory/L1 cache 570 can be used to cache reads and writes. One or moreof the shared memory/L1 cache 570, L2 cache 460, and memory 304 arebacking stores.

Combining data cache and shared memory functionality into a singlememory block provides the best overall performance for both types ofmemory accesses. The capacity is usable as a cache by programs that donot use shared memory. For example, if shared memory is configured touse half of the capacity, texture and load/store operations can use theremaining capacity. Integration within the shared memory/L1 cache 570enables the shared memory/L1 cache 570 to function as a high-throughputconduit for streaming data while simultaneously providing high-bandwidthand low-latency access to frequently reused data.

When configured for general purpose parallel computation, a simplerconfiguration can be used compared with graphics processing.Specifically, the fixed function graphics processing units shown in FIG.3, are bypassed, creating a much simpler programming model. In thegeneral purpose parallel computation configuration, the workdistribution unit 325 assigns and distributes blocks of threads directlyto the DPCs 420. The threads in a block execute the same program, usinga unique thread ID in the calculation to ensure each thread generatesunique results, using the SM 440 to execute the program and performcalculations, shared memory/L1 cache 570 to communicate between threads,and the LSU 554 to read and write global memory through the sharedmemory/L1 cache 570 and the memory partition unit 380. When configuredfor general purpose parallel computation, the SM 440 can also writecommands that the scheduler unit 320 can use to launch new work on theDPCs 420.

The PPU 300 may be included in a desktop computer, a laptop computer, atablet computer, servers, supercomputers, a smart-phone (e.g., awireless, hand-held device), personal digital assistant (PDA), a digitalcamera, a vehicle, a head mounted display, a hand-held electronicdevice, and the like. In an embodiment, the PPU 300 is embodied on asingle semiconductor substrate. In another embodiment, the PPU 300 isincluded in a system-on-a-chip (SoC) along with one or more otherdevices such as additional PPUs 300, the memory 204, a reducedinstruction set computer (RISC) CPU, a memory management unit (MMU), adigital-to-analog converter (DAC), and the like.

In an embodiment, the PPU 300 may be included on a graphics card thatincludes one or more memory devices 304. The graphics card may beconfigured to interface with a PCIe slot on a motherboard of a desktopcomputer. In yet another embodiment, the PPU 300 may be an integratedgraphics processing unit (iGPU) or parallel processor included in thechipset of the motherboard.

Exemplary Computing System

Systems with multiple GPUs and CPUs are used in a variety of industriesas developers expose and leverage more parallelism in applications suchas artificial intelligence computing. High-performance GPU-acceleratedsystems with tens to many thousands of compute nodes are deployed indata centers, research facilities, and supercomputers to solve everlarger problems. As the number of processing devices within thehigh-performance systems increases, the communication and data transfermechanisms need to scale to support the increased bandwidth.

FIG. 5B is a conceptual diagram of a processing system 500 implementedusing the PPU 300 of FIG. 3, in accordance with an embodiment. Theexemplary system 565 may be configured to implement the method 100 shownin FIG. 1. The processing system 500 includes a CPU 530, switch 510, andmultiple PPUs 300 each and respective memories 304. The NVLink 310provides high-speed communication links between each of the PPUs 300.Although a particular number of NVLink 310 and interconnect 302connections are illustrated in FIG. 5B, the number of connections toeach PPU 300 and the CPU 530 may vary. The switch 510 interfaces betweenthe interconnect 302 and the CPU 530. The PPUs 300, memories 304, andNVLinks 310 may be situated on a single semiconductor platform to form aparallel processing module 525. In an embodiment, the switch 510supports two or more protocols to interface between various differentconnections and/or links.

In another embodiment (not shown), the NVLink 310 provides one or morehigh-speed communication links between each of the PPUs 300 and the CPU530 and the switch 510 interfaces between the interconnect 302 and eachof the PPUs 300. The PPUs 300, memories 304, and interconnect 302 may besituated on a single semiconductor platform to form a parallelprocessing module 525. In yet another embodiment (not shown), theinterconnect 302 provides one or more communication links between eachof the PPUs 300 and the CPU 530 and the switch 510 interfaces betweeneach of the PPUs 300 using the NVLink 310 to provide one or morehigh-speed communication links between the PPUs 300. In anotherembodiment (not shown), the NVLink 310 provides one or more high-speedcommunication links between the PPUs 300 and the CPU 530 through theswitch 510. In yet another embodiment (not shown), the interconnect 302provides one or more communication links between each of the PPUs 300directly. One or more of the NVLink 310 high-speed communication linksmay be implemented as a physical NVLink interconnect or either anon-chip or on-die interconnect using the same protocol as the NVLink310.

In the context of the present description, a single semiconductorplatform may refer to a sole unitary semiconductor-based integratedcircuit fabricated on a die or chip. It should be noted that the termsingle semiconductor platform may also refer to multi-chip modules withincreased connectivity which simulate on-chip operation and makesubstantial improvements over utilizing a conventional busimplementation. Of course, the various circuits or devices may also besituated separately or in various combinations of semiconductorplatforms per the desires of the user. Alternately, the parallelprocessing module 525 may be implemented as a circuit board substrateand each of the PPUs 300 and/or memories 304 may be packaged devices. Inan embodiment, the CPU 530, switch 510, and the parallel processingmodule 525 are situated on a single semiconductor platform.

In an embodiment, the signaling rate of each NVLink 310 is 20 to 25Gigabits/second and each PPU 300 includes six NVLink 310 interfaces (asshown in FIG. 5B, five NVLink 310 interfaces are included for each PPU300). Each NVLink 310 provides a data transfer rate of 25Gigabytes/second in each direction, with six links providing 300Gigabytes/second. The NVLinks 310 can be used exclusively for PPU-to-PPUcommunication as shown in FIG. 5B, or some combination of PPU-to-PPU andPPU-to-CPU, when the CPU 530 also includes one or more NVLink 310interfaces.

In an embodiment, the NVLink 310 allows direct load/store/atomic accessfrom the CPU 530 to each PPU's 300 memory 304. In an embodiment, theNVLink 310 supports coherency operations, allowing data read from thememories 304 to be stored in the cache hierarchy of the CPU 530,reducing cache access latency for the CPU 530. In an embodiment, theNVLink 310 includes support for Address Translation Services (ATS),allowing the PPU 300 to directly access page tables within the CPU 530.One or more of the NVLinks 310 may also be configured to operate in alow-power mode.

FIG. 5C illustrates an exemplary system 565 in which the variousarchitecture and/or functionality of the various previous embodimentsmay be implemented. The exemplary system 565 may be configured toimplement the method 100 shown in FIG. 1.

As shown, a system 565 is provided including at least one centralprocessing unit 530 that is connected to a communication bus 575. Thecommunication bus 575 may be implemented using any suitable protocol,such as PCI (Peripheral Component Interconnect), PCI-Express, AGP(Accelerated Graphics Port), HyperTransport, or any other bus orpoint-to-point communication protocol(s). The system 565 also includes amain memory 540. Control logic (software) and data are stored in themain memory 540 which may take the form of random access memory (RAM).

The system 565 also includes input devices 560, the parallel processingsystem 525, and display devices 545, e.g. a conventional CRT (cathoderay tube), LCD (liquid crystal display), LED (light emitting diode),plasma display or the like. User input may be received from the inputdevices 560, e.g., keyboard, mouse, touchpad, microphone, and the like.Each of the foregoing modules and/or devices may even be situated on asingle semiconductor platform to form the system 565. Alternately, thevarious modules may also be situated separately or in variouscombinations of semiconductor platforms per the desires of the user.

Further, the system 565 may be coupled to a network (e.g., atelecommunications network, local area network (LAN), wireless network,wide area network (WAN) such as the Internet, peer-to-peer network,cable network, or the like) through a network interface 535 forcommunication purposes.

The system 565 may also include a secondary storage (not shown). Thesecondary storage 610 includes, for example, a hard disk drive and/or aremovable storage drive, representing a floppy disk drive, a magnetictape drive, a compact disk drive, digital versatile disk (DVD) drive,recording device, universal serial bus (USB) flash memory. The removablestorage drive reads from and/or writes to a removable storage unit in awell-known manner.

Computer programs, or computer control logic algorithms, may be storedin the main memory 540 and/or the secondary storage. Such computerprograms, when executed, enable the system 565 to perform variousfunctions. The memory 540, the storage, and/or any other storage arepossible examples of computer-readable media.

The architecture and/or functionality of the various previous figuresmay be implemented in the context of a general computer system, acircuit board system, a game console system dedicated for entertainmentpurposes, an application-specific system, and/or any other desiredsystem. For example, the system 565 may take the form of a desktopcomputer, a laptop computer, a tablet computer, servers, supercomputers,a smart-phone (e.g., a wireless, hand-held device), personal digitalassistant (PDA), a digital camera, a vehicle, a head mounted display, ahand-held electronic device, a mobile phone device, a television,workstation, game consoles, embedded system, and/or any other type oflogic.

While various embodiments have been described above, it should beunderstood that they have been presented by way of example only, and notlimitation. Thus, the breadth and scope of a preferred embodiment shouldnot be limited by any of the above-described exemplary embodiments, butshould be defined only in accordance with the following claims and theirequivalents.

Graphics Processing Pipeline

In an embodiment, the PPU 300 comprises a graphics processing unit(GPU). The PPU 300 is configured to receive commands that specify shaderprograms for processing graphics data. Graphics data may be defined as aset of primitives such as points, lines, triangles, quads, trianglestrips, and the like. Typically, a primitive includes data thatspecifies a number of vertices for the primitive (e.g., in a model-spacecoordinate system) as well as attributes associated with each vertex ofthe primitive. The PPU 300 can be configured to process the graphicsprimitives to generate a frame buffer (e.g., pixel data for each of thepixels of the display).

An application writes model data for a scene (e.g., a collection ofvertices and attributes) to a memory such as a system memory or memory304. The model data defines each of the objects that may be visible on adisplay. The application then makes an API call to the driver kernelthat requests the model data to be rendered and displayed. The driverkernel reads the model data and writes commands to the one or morestreams to perform operations to process the model data. The commandsmay reference different shader programs to be implemented on the SMs 440of the PPU 300 including one or more of a vertex shader, hull shader,domain shader, geometry shader, and a pixel shader. For example, one ormore of the SMs 440 may be configured to execute a vertex shader programthat processes a number of vertices defined by the model data. In anembodiment, the different SMs 440 may be configured to execute differentshader programs concurrently. For example, a first subset of SMs 440 maybe configured to execute a vertex shader program while a second subsetof SMs 440 may be configured to execute a pixel shader program. Thefirst subset of SMs 440 processes vertex data to produce processedvertex data and writes the processed vertex data to the L2 cache 460and/or the memory 304. After the processed vertex data is rasterized(e.g., transformed from three-dimensional data into two-dimensional datain screen space) to produce fragment data, the second subset of SMs 440executes a pixel shader to produce processed fragment data, which isthen blended with other processed fragment data and written to the framebuffer in memory 304. The vertex shader program and pixel shader programmay execute concurrently, processing different data from the same scenein a pipelined fashion until all of the model data for the scene hasbeen rendered to the frame buffer. Then, the contents of the framebuffer are transmitted to a display controller for display on a displaydevice.

FIG. 6 is a conceptual diagram of a graphics processing pipeline 600implemented by the PPU 300 of FIG. 3, in accordance with an embodiment.The graphics processing pipeline 600 is an abstract flow diagram of theprocessing steps implemented to generate 2D computer-generated imagesfrom 3D geometry data. As is well-known, pipeline architectures mayperform long latency operations more efficiently by splitting up theoperation into a plurality of stages, where the output of each stage iscoupled to the input of the next successive stage. Thus, the graphicsprocessing pipeline 600 receives input data 601 that is transmitted fromone stage to the next stage of the graphics processing pipeline 600 togenerate output data 602. In an embodiment, the graphics processingpipeline 600 may represent a graphics processing pipeline defined by theOpenGL® API. As an option, the graphics processing pipeline 600 may beimplemented in the context of the functionality and architecture of theprevious Figures and/or any subsequent Figure(s).

As shown in FIG. 6, the graphics processing pipeline 600 comprises apipeline architecture that includes a number of stages. The stagesinclude, but are not limited to, a data assembly stage 610, a vertexshading stage 620, a primitive assembly stage 630, a geometry shadingstage 640, a viewport scale, cull, and clip (VSCC) stage 650, arasterization stage 660, a fragment shading stage 670, and a rasteroperations stage 680. In an embodiment, the input data 601 comprisescommands that configure the processing units to implement the stages ofthe graphics processing pipeline 600 and geometric primitives (e.g.,points, lines, triangles, quads, triangle strips or fans, etc.) to beprocessed by the stages. The output data 602 may comprise pixel data(e.g., color data) that is copied into a frame buffer or other type ofsurface data structure in a memory.

The data assembly stage 610 receives the input data 601 that specifiesvertex data for high-order surfaces, primitives, or the like. The dataassembly stage 610 collects the vertex data in a temporary storage orqueue, such as by receiving a command from the host processor thatincludes a pointer to a buffer in memory and reading the vertex datafrom the buffer. The vertex data is then transmitted to the vertexshading stage 620 for processing.

The vertex shading stage 620 processes vertex data by performing a setof operations (e.g., a vertex shader or a program) once for each of thevertices. Vertices may be, e.g., specified as a 4-coordinate vector(e.g., <x, y, z, w>) associated with one or more vertex attributes(e.g., color, texture coordinates, surface normal, etc.). The vertexshading stage 620 may manipulate individual vertex attributes such asposition, color, texture coordinates, and the like. In other words, thevertex shading stage 620 performs operations on the vertex coordinatesor other vertex attributes associated with a vertex. Such operationscommonly including lighting operations (e.g., modifying color attributesfor a vertex) and transformation operations (e.g., modifying thecoordinate space for a vertex). For example, vertices may be specifiedusing coordinates in an object-coordinate space, which are transformedby multiplying the coordinates by a matrix that translates thecoordinates from the object-coordinate space into a world space or anormalized-device-coordinate (NCD) space. The vertex shading stage 620generates transformed vertex data that is transmitted to the primitiveassembly stage 630.

The primitive assembly stage 630 collects vertices output by the vertexshading stage 620 and groups the vertices into geometric primitives forprocessing by the geometry shading stage 640. For example, the primitiveassembly stage 630 may be configured to group every three consecutivevertices as a geometric primitive (e.g., a triangle) for transmission tothe geometry shading stage 640. In some embodiments, specific verticesmay be reused for consecutive geometric primitives (e.g., twoconsecutive triangles in a triangle strip may share two vertices). Theprimitive assembly stage 630 transmits geometric primitives (e.g., acollection of associated vertices) to the geometry shading stage 640.

The geometry shading stage 640 processes geometric primitives byperforming a set of operations (e.g., a geometry shader or program) onthe geometric primitives. Tessellation operations may generate one ormore geometric primitives from each geometric primitive. In other words,the geometry shading stage 640 may subdivide each geometric primitiveinto a finer mesh of two or more geometric primitives for processing bythe rest of the graphics processing pipeline 600. The geometry shadingstage 640 transmits geometric primitives to the viewport SCC stage 650.

In an embodiment, the graphics processing pipeline 600 may operatewithin a streaming multiprocessor and the vertex shading stage 620, theprimitive assembly stage 630, the geometry shading stage 640, thefragment shading stage 670, and/or hardware/software associatedtherewith, may sequentially perform processing operations. Once thesequential processing operations are complete, in an embodiment, theviewport SCC stage 650 may utilize the data. In an embodiment, primitivedata processed by one or more of the stages in the graphics processingpipeline 600 may be written to a cache (e.g. L1 cache, a vertex cache,etc.). In this case, in an embodiment, the viewport SCC stage 650 mayaccess the data in the cache. In an embodiment, the viewport SCC stage650 and the rasterization stage 660 are implemented as fixed functioncircuitry.

The viewport SCC stage 650 performs viewport scaling, culling, andclipping of the geometric primitives. Each surface being rendered to isassociated with an abstract camera position. The camera positionrepresents a location of a viewer looking at the scene and defines aviewing frustum that encloses the objects of the scene. The viewingfrustum may include a viewing plane, a rear plane, and four clippingplanes. Any geometric primitive entirely outside of the viewing frustummay be culled (e.g., discarded) because the geometric primitive will notcontribute to the final rendered scene. Any geometric primitive that ispartially inside the viewing frustum and partially outside the viewingfrustum may be clipped (e.g., transformed into a new geometric primitivethat is enclosed within the viewing frustum. Furthermore, geometricprimitives may each be scaled based on a depth of the viewing frustum.All potentially visible geometric primitives are then transmitted to therasterization stage 660.

The rasterization stage 660 converts the 3D geometric primitives into 2Dfragments (e.g. capable of being utilized for display, etc.). Therasterization stage 660 may be configured to utilize the vertices of thegeometric primitives to setup a set of plane equations from whichvarious attributes can be interpolated. The rasterization stage 660 mayalso compute a coverage mask for a plurality of pixels that indicateswhether one or more sample locations for the pixel intercept thegeometric primitive. In an embodiment, z-testing may also be performedto determine if the geometric primitive is occluded by other geometricprimitives that have already been rasterized. The rasterization stage660 generates fragment data (e.g., interpolated vertex attributesassociated with a particular sample location for each covered pixel)that are transmitted to the fragment shading stage 670.

The fragment shading stage 670 processes fragment data by performing aset of operations (e.g., a fragment shader or a program) on each of thefragments. The fragment shading stage 670 may generate pixel data (e.g.,color values) for the fragment such as by performing lighting operationsor sampling texture maps using interpolated texture coordinates for thefragment. The fragment shading stage 670 generates pixel data that istransmitted to the raster operations stage 680.

The raster operations stage 680 may perform various operations on thepixel data such as performing alpha tests, stencil tests, and blendingthe pixel data with other pixel data corresponding to other fragmentsassociated with the pixel. When the raster operations stage 680 hasfinished processing the pixel data (e.g., the output data 602), thepixel data may be written to a render target such as a frame buffer, acolor buffer, or the like.

It will be appreciated that one or more additional stages may beincluded in the graphics processing pipeline 600 in addition to or inlieu of one or more of the stages described above. Variousimplementations of the abstract graphics processing pipeline mayimplement different stages. Furthermore, one or more of the stagesdescribed above may be excluded from the graphics processing pipeline insome embodiments (such as the geometry shading stage 640). Other typesof graphics processing pipelines are contemplated as being within thescope of the present disclosure. Furthermore, any of the stages of thegraphics processing pipeline 600 may be implemented by one or morededicated hardware units within a graphics processor such as PPU 300.Other stages of the graphics processing pipeline 600 may be implementedby programmable hardware units such as the SM 440 of the PPU 300.

The graphics processing pipeline 600 may be implemented via anapplication executed by a host processor, such as a CPU. In anembodiment, a device driver may implement an application programminginterface (API) that defines various functions that can be utilized byan application in order to generate graphical data for display. Thedevice driver is a software program that includes a plurality ofinstructions that control the operation of the PPU 300. The API providesan abstraction for a programmer that lets a programmer utilizespecialized graphics hardware, such as the PPU 300, to generate thegraphical data without requiring the programmer to utilize the specificinstruction set for the PPU 300. The application may include an API callthat is routed to the device driver for the PPU 300. The device driverinterprets the API call and performs various operations to respond tothe API call. In some instances, the device driver may performoperations by executing instructions on the CPU. In other instances, thedevice driver may perform operations, at least in part, by launchingoperations on the PPU 300 utilizing an input/output interface betweenthe CPU and the PPU 300. In an embodiment, the device driver isconfigured to implement the graphics processing pipeline 600 utilizingthe hardware of the PPU 300.

Various programs may be executed within the PPU 300 in order toimplement the various stages of the graphics processing pipeline 600.For example, the device driver may launch a kernel on the PPU 300 toperform the vertex shading stage 620 on one SM 440 (or multiple SMs440). The device driver (or the initial kernel executed by the PPU 400)may also launch other kernels on the PPU 400 to perform other stages ofthe graphics processing pipeline 600, such as the geometry shading stage640 and the fragment shading stage 670. In addition, some of the stagesof the graphics processing pipeline 600 may be implemented on fixed unithardware such as a rasterizer or a data assembler implemented within thePPU 400. It will be appreciated that results from one kernel may beprocessed by one or more intervening fixed function hardware unitsbefore being processed by a subsequent kernel on an SM 440.

Machine Learning

Deep neural networks (DNNs) developed on processors, such as the PPU 300have been used for diverse use cases, from self-driving cars to fasterdrug development, from automatic image captioning in online imagedatabases to smart real-time language translation in video chatapplications. Deep learning is a technique that models the neurallearning process of the human brain, continually learning, continuallygetting smarter, and delivering more accurate results more quickly overtime. A child is initially taught by an adult to correctly identify andclassify various shapes, eventually being able to identify shapeswithout any coaching. Similarly, a deep learning or neural learningsystem needs to be trained in object recognition and classification forit get smarter and more efficient at identifying basic objects, occludedobjects, etc., while also assigning context to objects.

At the simplest level, neurons in the human brain look at various inputsthat are received, importance levels are assigned to each of theseinputs, and output is passed on to other neurons to act upon. Anartificial neuron or perceptron is the most basic model of a neuralnetwork. In one example, a perceptron may receive one or more inputsthat represent various features of an object that the perceptron isbeing trained to recognize and classify, and each of these features isassigned a certain weight based on the importance of that feature indefining the shape of an object.

A deep neural network (DNN) model includes multiple layers of manyconnected perceptrons (e.g., nodes) that can be trained with enormousamounts of input data to quickly solve complex problems with highaccuracy. In one example, a first layer of the DLL model breaks down aninput image of an automobile into various sections and looks for basicpatterns such as lines and angles. The second layer assembles the linesto look for higher level patterns such as wheels, windshields, andmirrors. The next layer identifies the type of vehicle, and the finalfew layers generate a label for the input image, identifying the modelof a specific automobile brand.

Once the DNN is trained, the DNN can be deployed and used to identifyand classify objects or patterns in a process known as inference.Examples of inference (the process through which a DNN extracts usefulinformation from a given input) include identifying handwritten numberson checks deposited into ATM machines, identifying images of friends inphotos, delivering movie recommendations to over fifty million users,identifying and classifying different types of automobiles, pedestrians,and road hazards in driverless cars, or translating human speech inreal-time.

During training, data flows through the DNN in a forward propagationphase until a prediction is produced that indicates a labelcorresponding to the input. If the neural network does not correctlylabel the input, then errors between the correct label and the predictedlabel are analyzed, and the weights are adjusted for each feature duringa backward propagation phase until the DNN correctly labels the inputand other inputs in a training dataset. Training complex neural networksrequires massive amounts of parallel computing performance, includingfloating-point multiplications and additions that are supported by thePPU 300. Inferencing is less compute-intensive than training, being alatency-sensitive process where a trained neural network is applied tonew inputs it has not seen before to classify images, translate speech,and generally infer new information.

Neural networks rely heavily on matrix math operations, and complexmulti-layered networks require tremendous amounts of floating-pointperformance and bandwidth for both efficiency and speed. With thousandsof processing cores, optimized for matrix math operations, anddelivering tens to hundreds of TFLOPS of performance, the PPU 300 is acomputing platform capable of delivering performance required for deepneural network-based artificial intelligence and machine learningapplications.

What is claimed is:
 1. A method, comprising: receiving input associatedwith workloads executed on a chip having two or more hardware componentsthat operate under a shared power constraint, the input including:descriptions of the workloads, performance metrics of each of the two ormore hardware components when executing each of the workloads, and powerconsumption metrics for each of the workloads; training an artificialintelligence (AI) network that correlates the descriptions of theworkloads, the performance metrics for each of the workloads, and thepower consumption by each of the workloads; receiving a selection of anoptimization mode for the chip that considers both performance and powerconsumption; determining using the AI network an optimal operating pointof the chip, according to the selected optimization mode; andconfiguring the chip to operate at the determined optimal operatingpoint.
 2. The method of claim 1, wherein the two or more hardwarecomponents include memory and a processor.
 3. The method of claim 2,wherein the memory is DRAM and the processor is a GPU.
 4. The method ofclaim 1, wherein the input is accumulated by capture logic over apredefined window of time.
 5. The method of claim 4, wherein forgraphics workloads, the input is captured over an entire frame.
 6. Themethod of claim 4, wherein for compute or deep learning workloads, theinput is captured at a function call level or over a fixed period oftime.
 7. The method of claim 1, wherein each of the descriptions of theworkloads includes at least one of: an indication of an applicationexecuting a workload, operations performed within the workload, or dataon which the workload is performed.
 8. The method of claim 1, whereinthe performance metrics include a frame time.
 9. The method of claim 1,wherein the performance metrics include instructions per second.
 10. Themethod of claim 1, wherein the power consumption metrics for each of theworkloads includes an amount of power consumed by each hardwarecomponent to perform the workload.
 11. The method of claim 1, whereinthe power consumption metrics for each of the workloads includes a totalamount of power consumed by the two or more hardware components toperform the workload.
 12. The method of claim 1, wherein the selectionof the optimization mode for the chip indicates: a parameter for whichto optimize operation of the chip, the parameter being one ofperformance, power, or efficiency.
 13. The method of claim 12, whereindetermining the optimal operating point of the chip, according to theselected optimization mode, includes: when the selected optimizationmode is to optimize operation of the chip for performance: identifyingthe target value for the performance, identifying a power threshold,using the AI network to determine the optimal operating point for thechip to maximize performance without exceeding the power threshold, theoptimal operating point for the chip including operating states for eachhardware component of the two or more hardware components and a voltagestate for the two or more hardware components.
 14. The method of claim12, wherein determining the optimal operating point of the chip,according to the selected optimization mode, includes: when the selectedoptimization mode is to optimize operation of the chip for power:identifying the target value for the power, identifying a performancethreshold, using the AI network to determine the optimal operating pointfor the chip to minimize power consumption without falling below theperformance threshold, the optimal operating point for the chipincluding operating states for each hardware component of the two ormore hardware components and a voltage state for the two or morehardware components.
 15. The method of claim 12, wherein determining theoptimal operating point of the chip, according to the selectedoptimization mode, includes: when the selected optimization mode is tooptimize operation of the chip for efficiency: identifying an efficiencythreshold, wherein the efficiency threshold is defined based on a changein performance in relation to a change in power consumption, using theAI network to determine the optimal operating point for the chip tomaximize performance without falling below the efficiency threshold, theoptimal operating point for the chip including operating states for eachhardware component of the two or more hardware components and a voltagestate for the two or more hardware components.
 16. The method of claim1, wherein the optimal operating point of the chip includes operatingstates for each hardware component of the two or more hardwarecomponents, the operating states including clock frequencies for eachhardware component of the two or more hardware components and a voltagestate for the two or more hardware components.
 17. The method of claim1, where the optimal operating point of the chip is determined based ona description of one or more prior workloads executed by the chip, andis employed when executing a subsequent workload on the chip.
 18. Themethod of claim 1, wherein the determining of the optimal operatingpoint of the chip and the configuring the chip to operate at thedetermined optimal operating point are repeated: for each new workloadexecuted on the chip, or during workload execution at various predefinedoperating points within an application.
 19. The method of claim 1,wherein the determining of the optimal operating point of the chip andthe configuring the chip to operate at the determined optimal operatingpoint are performed by software executed by a CPU of the chip.
 20. Themethod of claim 1, wherein the determining of the optimal operatingpoint of the chip and the configuring the chip to operate at thedetermined optimal operating point are performed by dedicated hardwareon the chip.
 21. A non-transitory computer readable medium storing codeexecutable by a processor to perform a method comprising: receivinginput associated with workloads executed on a chip having two or morehardware components that operate under a shared power constraint, theinput including: descriptions of the workloads, performance metrics ofeach of the two or more hardware components when executing each of theworkloads, and power consumption metrics for each of the workloads;training an artificial intelligence (AI) network that correlates thedescriptions of the workloads, the performance metrics for each of theworkloads, and the power consumption by each of the workloads; receivinga selection of an optimization mode for the chip that considers bothperformance and power consumption; determining using the AI network anoptimal operating point of the chip, according to the selectedoptimization mode; and configuring the chip to operate at the determinedoptimal operating point.
 22. The non-transitory computer readable mediumof claim 21, wherein the two or more hardware components include memoryand a processor.
 23. The non-transitory computer readable medium ofclaim 21, wherein the optimal operating point of the chip includesoperating states for each hardware component of the two or more hardwarecomponents, the operating states including clock frequencies for eachhardware component of the two or more hardware components and a voltagestate for the two or more hardware components.
 24. The non-transitorycomputer readable medium of claim 21, where the optimal operating pointof the chip is determined based on a description of one or more priorworkloads executed by the chip, and is employed when executing asubsequent workload on the chip.
 25. The non-transitory computerreadable medium of claim 21, wherein the determining of the optimaloperating point of the chip and the configuring the chip to operate atthe determined optimal operating point are repeated: for each newworkload executed on the chip, or during workload execution at variouspredefined operating points within an application.
 26. A chip,comprising: two or more hardware components that operate under a sharedpower constraint; and dedicated hardware for: receiving input associatedwith workloads executed on the chip, the input including: descriptionsof the workloads, performance metrics of each of the two or morehardware components when executing each of the workloads, and powerconsumption metrics for each of the workloads; training an artificialintelligence (AI) network that correlates the descriptions of theworkloads, the performance metrics for each of the workloads, and thepower consumption by each of the workloads; receiving a selection of anoptimization mode for the chip that considers both performance and powerconsumption; determining using the AI network an optimal operating pointof the chip, according to the selected optimization mode; andconfiguring the chip to operate at the determined optimal operatingpoint.
 27. The chip of claim 26, wherein the two or more hardwarecomponents include memory and a processor.
 28. The chip of claim 26,wherein the optimal operating point of the chip includes operatingstates for each hardware component of the two or more hardwarecomponents, the operating states including clock frequencies for eachhardware component of the two or more hardware components and a voltagestate for the two or more hardware components.
 29. The chip of claim 26,where the optimal operating point of the chip is determined based on adescription of one or more prior workloads executed by the chip, and isemployed when executing a subsequent workload on the chip.
 30. The chipof claim 26, wherein the determining of the optimal operating point ofthe chip and the configuring the chip to operate at the determinedoptimal operating point are repeated: for each new workload executed onthe chip, or during workload execution at various predefined operatingpoints within an application.